It is known that simultaneously biasing the gate of a transistor and its groundplane improves transistor performance, at least in the static regime. The term groundplane generally refers to an isolated n-doped or p-doped region in a semiconductor, it may also be defined by the term well. Such transistors are thus called “double-gate” transistors.
The performance, in terms of current as a function of voltage, obtained with a single-gate transistor and with a double-gate transistor has in particular been described in the article “Low Leakage and Low Variability Ultra-Thin Body and Buried Oxide (UT2B) SOI Technology for 20 nm Low Power CMOS and Beyond”, F. Andrieu, O. Weber, J. Mazurier, O. Thomas, J-P. Noel, C. Fenouillet-Béranger, J-P. Mazellier, P. Perreau, T. Poiroux, Y. Morand*, T. Morel, S. Allegret*, V. Loup, S. Barnola, F. Martin, J-F. Damlencourt, I. Servin, M. Cassé, X. Garros, O. Rozeau, M-A. Jaud, G. Cibrario, J. Cluzel, A. Toffoli, F. Allain, R. Kies, D. Lafond, V. Delaye, C. Tabone, L. Tosti, L. Brévard, P. Gaud, V. Paruchuri#, K. K. Bourdelle+, W. Schwarzenbach+, O. Bonnin+, B-Y. Nguyen+, B. Doris#, F. Boeuf*, T. Skotnicki*, O. Faynot, CEA-LETI Minatec, 17 rue des Martyrs, 38054 Grenoble Cedex 9, France, ST Microelectronics, 850 rue Monnet, F-38926 Crones; # IBM Research, Albany, N.Y. 12203; + SOITEC, Parc Technologiques des Fontaines F-38926 Bernin, 978-1-4244-7641-1/10/$26.00 ©2010 IEEE 2010 Symposium on VLSI Technology Digest of Technical Papers. FIG. 1 thus shows the performance obtained (the curves “dash: SG mode” relate to a single-gate configuration, and the curves “full: DG mode” relate to a double-gate configuration).
SRAM memories may in particular be improved with this operating mode.
Configurations allowing sets of pMOS and nMOS transistors to be addressed have also been proposed, as in the article: “UTBB FDSOI transistors with dual STI fora multi-Vt strategy at 20 nm node and below” L. Grenouillet1, M. Vinet1, J. Gimbert2, B. Giraud1, J. P. Noël2, Q. Liu2, P. Khare2, M. A. Jaud1, Y. Le Tiec1, R. Wacquez1, T. Levin3, P. Rivallin1, S. Holmes3, S. Liu3, K. J. Chen3, O. Rozeau1, P. Scheiblin1, E. McLellan3, M. Malley3, J. Guilford3, A. Upham3, R. Johnson3, M. Hargrove4, T. Hook3, S. Schmitz3, S. Mehta3, J. Kuss3, N. Loubet2, S. Teehan3, M. Terrizzi3, S. Ponoth3, K. Cheng3, T. Nagumo5, A. Khakifirooz3, F. Monsieur2, P. Kulkarni3, R. Conte3, J. Demarest3, O. Faynot1, W. Kleemeier2, S. Luning4, B. Doris3, 1CEA-LETI, 2STMicroelectronics, 3IBM, 4GLOBALFOUNDRIES, 5Renesas, 257 Fuller Rd, 12203 Albany, N.Y., USA, 978-1-4673-4871-3/12/$31.00 ©2012 IEEE.
Generally, it is necessary to make provision, in order for the various transistors to operate, to electrically isolate them from one another. For this reason, the transistors are generally encircled by trench isolations that are designated by the acronym STI for “shallow trench isolation”. In the article by L. Grenouillet et al., it is proposed, as illustrated in FIG. 4 of this article and reproduced in FIG. 2 of the present patent application, to produce deep STI isolations between the nMOS transistors and the pMOS transistors in order to isolate their wells, and shallow STIs between MOS transistors of the same type, in order to isolate the active (source/drain) regions of the transistors.